1. Field of the Invention
The present invention relates to systems for storing and accessing data. In particular, the invention provides a system for storing data associated with multiple addresses in a storage element.
2. Background
Buffers, caches, and other high-speed memory devices may be used in processor-based systems to improve overall system performance. In particular, data access speed is increased by constructing buffers and caches using high-speed memories. A buffer or cache provides a temporary storage location for data or instructions that are expected to be required by the processor in the near future. Caches and buffers are often manufactured from fast memories such as static random-access memory (SRAM) to provide faster access than a typical dynamic random-access memory (DRAM). Thus, the processor can access data stored in an SRAM-based cache or buffer faster than accessing the same data from a DRAM.
Various known computer systems include a tag SRAM array that functions as a look-up table for addresses stored in the array. The look-up table addresses correspond to each separate data address in the cache. Each address is stored in a separate entry in the SRAM array, referred to as a tag. Thus, the tag array is capable of identifying the data currently stored in the cache memory.
As data is stored in the cache or buffer, the main memory address is stored in the tag array. When a memory request is received from a processor or other device, the requested address is compared with the entries in the tag SRAM. If the requested address matches an address stored in the tag SRAM, then the data is retrieved from the cache or buffer. If the requested address does not match any entry in the tag SRAM, then the data is retrieved from main memory.
Caches and buffers may be arranged such that multiple data entries are stored in a single cache line or buffer line. In this situation, a separate address must be provided for each entry. Typically, a high-speed memory device is used to store these addresses. The use of multiple address tags requires additional memory storage space for the multiple address tags. However, the additional tag storage space is under utilized when a single data entry is stored in the cache line. This approach represents an inefficient use of the high-speed memory used to store address tags.
Alternatively, a particular cache line or buffer may be restricted to storing a single data entry, thereby requiring storage space for a single address tag. However, this may result in a partially empty cache line or buffer if the size of the stored data is smaller than the cache line capacity. This under utilization of the high-speed SRAM cells represents an inefficient use of memory resources.
Therefore, it is desirable to provide a system for storing data associated with multiple addresses in a storage element without requiring a significant increase in the size of the memory required to match the address tags.